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Alpha 21264
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#	Item
21	Alpha[removed]EV67 Microprocessor Hardware Reference Manual Order Number: DS–0028C–TE This manual is directly derived from the internal[removed]EV67 Specifications, Revision 1.5. You can access this hardware reference m Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:51 Computer engineering DEC Alpha Alpha 21264 PALcode CPU cache Processor register Instruction set Computer architecture Computer hardware Central processing unit
22	AlphaPC 264DP AlphaPC 264DP Product Brief By offering unrivaled performance, the AlphaPC 264DP motherboard provides an easy, cost-effective solution for companies developing high-performance Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:14 IBM PC compatibles Computer architecture Alpha 21264 Industry Standard Architecture Conventional PCI Expansion card DEC Alpha Daughterboard Acer Laboratories Incorporated Computer hardware Computer buses Computing
23	Alpha[removed]EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal[removed]EV6 Specifications, Revision 4.5. You can access this hardware reference manu Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:20 Computer engineering DEC Alpha PALcode Alpha 21264 CPU cache Branch predictor Processor register Instruction set Computer architecture Computer hardware Central processing unit
24	ReCycle: Pipeline Adaptation to Tolerate Process Variation∗ Abhishek Tiwari, Smruti R. Sarangi and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-11 01:31:00 Electronic engineering Central processing unit Pipeline Hazard Clock distribution network Clock skew Alpha 21264 CPU cache Computer architecture Computer hardware Clock signal
25	21264/EV68CB and[removed]EV68DC Hardware Reference Manual Part Number: DS–0031C–TE This manual is directly derived from the internal[removed]EV68CB and[removed]EV68DC Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:02:21 Instruction set architectures DEC Alpha Computer memory PALcode CPU cache ARM architecture Processor register Instruction set Computer architecture Computer hardware Central processing unit
26	Alpha[removed]Digital Semiconductor[removed]Alpha Microprocessor Product Brief Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:35 Alpha 21164 CPU cache DEC Alpha Alpha 21064 Alpha 21264 Computer hardware Computer architecture Instruction set architectures
27	In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. High Performance and Energy Efficient Serial Prefetch Architecture Glenn Reinman Brad Caldery Add to Reading List Source URL: cseweb.ucsd.edu Language: English - Date: 2002-06-24 03:41:14 Cache Computing Computer memory CPU cache Instruction prefetch Branch predictor Alpha 21264 Microarchitecture Pentium Pro Computer hardware Computer architecture Central processing unit
28	Speculative Updates of Local and Global Branch History: A Quantitative Analysis Kevin Skadron SKADRON @ CS . VIRGINIA . EDU Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-06-05 15:33:55 Central processing unit Instruction set architectures Branch predictor Alpha 21264 CPU cache Out-of-order execution Register renaming Microarchitecture DEC Alpha Computer architecture Computer engineering Computer hardware
29	Improving Application Performance by Dynamically Trading Frequency for Complexity in a GALS Microprocessor∗ Greg Semeraro, David H. Albonesi, Steven Dropsho, Grigorios Magklis, and Michael L. Scott URCS Technical Repor Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-02-12 17:49:46 Cache Computing CPU cache Computer memory Microprocessors Alpha 21264 Microarchitecture Branch predictor R8000 Computer hardware Computer architecture Central processing unit
30	10th Intl. Symp. on Asynchronous Circuits and Systems (ASYNC), Herakleion, Crete, Apr[removed]Hiding Synchronization Delays in a GALS Processor Microarchitecture∗ Greg Semeraro? , David H. Albonesi‡ , Grigorios Magklis Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-01 00:06:22 Central processing unit Alpha 21264 CPU cache Cycles per instruction Superscalar Microarchitecture Parallel computing FIFO Instruction set Computer architecture Computer hardware Computing

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